The invention relates to electronic apparatus having a common backplane which includes connectors for coupling to active modules implemented on circuit boards with edge connectors. In particular, electronic circuits may be simulated using such an architecture.
Note, at this point, that the discussion which follows will concern itself both with (i) physically implemented electronic circuitry, making up active modules (such as simulation modules) on circuit boards, and (ii) "logical" or "virtual" circuits whose simulation is the objective of the physical circuits. It is believed that, with this distinction in mind, the reader of this patent application will be able to tell, from the context, which circuit is being referred to at any given point. However, where further emphasis of this distinction is deemed necessary for clarity, terminology such as that just given will be used.
Where a circuit (a logical circuit, that is) is to be simulated, it has been conventional practice to partition the circuit into portions, and to use different simulator modules (physical circuitry) to simulate respective ones of the portions of the circuit.
The term "backplane" is conventionally used to refer to any structure for interconnecting the modules. More specifically, a "simulation backplane" is used for interconnecting simulator modules.
Sometimes, but not necessarily, the simulator system pay be physically configured as a set of simulator modules, on respective circuit boards, commonly housed in a chassis having a physical backplane structure for interconnecting the simulator boards. Where this sort of physical structure is not used, it is nevertheless common practice to use the term "simulation backplane" in a metaphorical sense. For the purpose of the present patent application, the term "simulation backplane," or the like, is construed broadly to cover all usage, physical, literal, or otherwise, which would be understood by a person skilled in the art.
A simulation backplane is essentially a parallel processing framework, where several simulators can concurrently solve a partitioned design. An example of a partitioned design is an electronic circuit design. The circuit is divided into portions, or modules. Thus, points or nodes which are on the interior of the overall circuit will, in some cases, be interface points between different portions of the circuit.
In a simulation backplane, each active module is assigned a portion of a partitioned design problem. The term "solver" will be used herein, to denote a process which may run on a processor, and which performs the simulation calculation of a portion of a partitioned design. Thus, a simulation backplane is typically comprised of a plurality of such processors, each running a respective solver process to perform simulation calculations for a respective portion of the partitioned design.
Each of the simulators may use a different level of modeling abstraction and time granularity.
Associated with the backplane, there is a synchronizing algorithm responsible for managing the progress of each solver, and for communicating the calculated waveforms. Synchronization, or integration, of the operations of the different simulators is an important part of the task of simulator system.
Toward this end, a key goal in simulation backplane technology is to reduce the cost of integration of proprietary simulation engines and utility tools to the benefit of both CAD (computer-aided design) vendors and circuit designers. Efforts have been made to develop a standard Application Programming Interface (API) that can be used in coordinating multiple simulators (digital, analog, and mixed signal) in a unified way.
One of the most difficult issues in this regard is the coupling of analog simulators which use a variety of different modeling techniques and disparate numerical solution models. To be useful, parallel processing must allow for a certain amount of cooperation and communication between processors, or else the system is merely an aggregation of independent processors.
A conventional processing architecture has included a plurality of processors and a communication manager, coupled between the processors to provide the results from one processor to another processor whose task requires having those results. A communication manager allows a first simulator to run until it reaches a given state, and then to pass that state on to a second simulator.
An example of such a parallel processor architecture for performing circuit simulation is given in Bischoff et al., U.S. Pat. No. 5,157,778, "Method and Apparatus for Circuit Simulation Using Parallel Processors Including Memory Arrangements and Matrix Decomposition Synchronization." That patent provides a description of a matrix structure for storing preliminary process data and results of calculations, thus providing access, by the processors, to the data without requiring a locking mechanism. Note, however, that data must be calculated by one processor before it can be passed, through the matrix, to another processor.
The Bischoff system, which involves a communication manager that simply allows one simulator to pass its state to a second simulator, produces results which are undesirably low in accuracy, and which may even be incorrect.
Another conventional approach is given in Vlach, U.S. Pat. No. 4,985,860, "Mixed-Mode-Simulation Interface." The Vlach patent describes a mixed-mode simulator, in which analog and digital portions of a simulator are synchronized. The Background section of the Vlach patent summarizes a conventional synchronization technique of making discrete time steps in a jointly determined, lockstep fashion. Vlach then presents his inventive system, in which a simulator has an analog portion and an event-driven portion. The analog portion runs the simulation until a threshold-crossing event occurs. That simulation is run based on polynomial interpolation. Vlach characterizes this as "`peeking` at the future."
Then, the event-driven portion operates on a step size determined from the threshold-crossing event. Vlach characterizes this portion as a "time rollback," in which the event-driven simulation is "always catching up" to the next time point.
The Vlach system, accordingly, takes less than optimal advantage of the efficiency which parallel processing potentially can provide, because of the added processing time consumed in the peeking, rolling back, and catching up.
Therefore, there remains an unfulfilled need for new, creative approaches to parallel simulator architecture, which will overcome these drawbacks to provide greater accuracy and efficiency.